Thanks a lot for the invitation here and I want to talk today a little bit on the problems
in multicore systems from a memory perspective.
What I want to talk in the next 45 minutes, I think you know everybody on the world is
working how to find solutions for the increasing computing demand and especially on the power
efficiency.
And there are one more traditional solution, these are heterogeneous multicore architectures
with dedicated accelerators, this is one option.
And then I would say more revolutionary approach is the invasive computing where you all are
working here.
But we should not forget that there are other very, very big challenges and they are becoming
more and more important and this is not the computation, it's the bandwidth and it's
the memory itself.
And I want to talk on these issues today since I guess you had here many presentations more
from a computing point of view and I want to focus here more on the memory and bandwidth.
I have two parts.
The first one is related to matrix, if you want to make a design space exploration, you
need appropriate matrix and I'm working for many years in wireless baseband processing
and I think this is one of the most growing areas.
Therefore I will take an example from wireless baseband processing and will show the impact
of memory and data transfers on such matrix.
This work was done in a cooperation with the UMIC excellence research cluster at the RWTH
Aachen and the second part, it's different.
I will look more on a larger scale.
I will look on the interface to the outside world and what we are currently seeing is
that we see more and more research in the field of 3D and I want to discuss 3D memories
and memory controllers.
I think you all know that we are living in a communication centric world and wireless
communication has completely changed the way how we are communicating today with our IT
infrastructure and also if you are looking on the market, then the wireless market is
the fastest market currently from a growing perspective and I had some discussions last
week, I was impressed and it seems that if you are looking on the revenue of wireless,
it's now becoming larger than the processor market of Intel.
Therefore we see currently a complete change and the race goes on.
If you are looking on the requirements, then we have a new cellular mode every three years,
a new frequency band is added every year and a continuous demand for higher data rates.
I want to look now only on the digital part of a mobile on the receiver structure where
you have your antenna, you have an RF front end, then you have a so-called inner receiver
where you make an estimation on the channel conditions, the parameters and then you have
the outer receiver.
In this metric issue I want to discuss here will be now done in the context of this basement
receivers.
If you are looking on the current digital computation load in a 3.5G smartphone, then
you have about 100 giga op and for a smartphone the total power consumption we have is limited
to 3 watt and this will not change.
We have one watt for digital signal processing, one watt for the display and then one watt
for all this analog stuff, power amplifier.
If you are now looking how the distribution of the workload is, you see the largest part
is the baseband which you as a user don't see.
This is what you expect from your mobile.
If you are now looking how this is distributed, then you see that the outer receiver is the
Presenters
Prof. Dr. Norbert Wehn
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Dauer
00:54:00 Min
Aufnahmedatum
2012-02-17
Hochgeladen am
2012-02-21 16:23:44
Sprache
de-DE
The race for increasing computing performance implied a dramatic increase in power which represents the main wall for further increase in computing. The “multi-core revolution” has shown a way out. Thus, today’s state-of-the-art architectures in embedded computing are based on heterogeneous multi-core architectures with application specific optimized accelerators. Unfortunately the immense computing power of such multi-core architectures brings as negative effect an increased demand on bandwidth and memory, denoted as bandwidth and memory walls. In this talk we will discuss two topics strongly related to the memory and bandwidth wall. First, the impact of memories and data transfers on metrics to compare different algorithms and implementations in the context of wireless baseband processing architectures. Second, the design space and potential of 3D DRAM architectures and multi-channel DRAM controllers.